The present invention relates, in general, to semiconductor devices and, more particularly, to interconnect structures and methods of layout therefor that reduce electromigration at localized regions of high current density so that interconnect reliability is increased.
Electromigration-related reliability failures continue to be a problem as semiconductor device geometries shrink into the sub-micron range and current densities within these devices continue to increase. As a result of these trends, electromigration-related reliability is becoming sufficiently critical that the two-dimensional design layout, and particularly the interconnect layout, of semiconductor devices is increasingly dictated in part by factors associated with the reduction of electromigration. Interconnect structures carrying high current density in prior semiconductor devices have exhibited electromigration failure at regions of high localized current density, such as at the edges joining aluminum interconnect runs to vias between multi-level interconnects, at contacts between metal interconnects, and in geometrical inhomogeneities in local, silicon substrate interconnect runs. Accordingly, it is desirable to have a semiconductor device with an interconnect layout structure that reduces premature failure due to electromigration at regions of high localized current density.